Logic Obfuscation Through Enhanced Threshold Voltage Defined Logic Family

The AMS Lab has developed a family of logic devices that are resistant against optical reverse engineering. Our threshold voltage device logic family, coined E-TVD, achieves 40% less power, 45% speed improvement and 34% smaller footprint when compared to conventional TVD designs.




Reverse engineering reveals the physical structure as well as the functionality of an intellectual property (IP) and integrated circuit (IC). This opens the door for IP/IC piracy, counterfeiting, and malicious attacks such as Trojan insertions. Camouflaged logic gates that have the same schematic architecture with identical layout is used to operate for different types of Boolean functions to prevent the de-layering of the chip. An enhanced threshold voltage (E-TVD) defined logic family is proposed in this brief that prevents the internal functionality from being revealed. Compared to previous TVD logic family, the total number of transistors and the cascaded transistors from supply to ground is reduced to enhance the overall performance. A 65nm process is used to compare the conventional TVD logic family and the proposed E-TVD logic family. Post layout simulation results show that the proposed E-TVD logic family for a 3-input logic gate is 34% area efficient, 45% faster, and consumes 40% less power compared to conventional TVD design.


DOI: 10.1109/TCSII.2020.2993447